fixed cache writeback, toggable clock intr

@@ -61,7 +61,12 @@ class Cache (object) :
             line = self.lru[-1]
             if line in self.new :
                 self.new.remove(line)
-                await self.writeback(block, line)
+                for b, l in self.tag.items() :
+                    if l == line :
+                        await self.writeback(b, line)
+                        break
+                else :
+                    assert False
             await self.load(block, line)
         await event("cache.hit", block, line)
         self.lru = [line] + [l for l in self.lru if l != line]
@@ -96,10 +101,11 @@ class Cache (object) :
 
 class CPU (object) :
     #REGS BP CR IR MR IP SP
-    def __init__ (self, cache=False) :
+    def __init__ (self, cache=False, clock=True) :
         self.reg = [0] * WSIZE
         self.intr = [0] * WSIZE
         self.clock = 0
+        self.clock_intr = clock
         self.halted = True
         self.cache = Cache(self) if cache else None
     ##
@@ -429,7 +435,7 @@ class CPU (object) :
     @trace("cpu.cycle.clock")
     async def clock_tick (self) :
         self.clock += 1
-        if self.clock == CLOCK_MOD :
+        if self.clock_intr and self.clock == CLOCK_MOD :
             self.clock = 0
             await self.setintr(IRQ_CLOCK)
         return self.clock

@@ -46,6 +46,7 @@ bios = window.CodeMirror.fromTextArea(_bios, {
 
 options = {"screen" : [True,  "Run TTC with a screen"],
            "cache" :  [False, "Run TTC with a cache"],
+           "clock" :  [True,  "Enable clock interrupt"],
            "boot" :   [False, "Boot TTC automatically"]}
 
 def on_toggle (event) :
@@ -216,7 +217,7 @@ def on_change (cm, change) :
 
 edit.on("change", on_change)
 
-def start_simul (rom, boot=0, cache=0, screen=1, ram=["0000:FFFF"]) :
+def start_simul (rom, boot=0, cache=0, clock=1, screen=1, ram=["0000:FFFF"]) :
     if errors :
         window.alert("you must fix errors first")
         return
@@ -224,6 +225,7 @@ def start_simul (rom, boot=0, cache=0, screen=1, ram=["0000:FFFF"]) :
     storage[name] = " ".join(rom)
     opts = "&".join([f"boot={int(bool(boot))}",
                      f"cache={int(bool(cache))}",
+                     f"clock={int(bool(clock))}",
                      f"screen={int(bool(screen))}"]
                     + [f"ram={quote(r)}" for r in ram])
     window.open(f"simul.html?id={name}&{opts}", "_blank")

@@ -2,9 +2,9 @@ from .cpu import CPU
 from .dev import Bus, RAM, Screen
 
 class TTC (object) :
-    def __init__ (self, bios, screen=True, cache=False) :
+    def __init__ (self, bios, screen=True, cache=False, clock=True) :
         onbus = []
-        self.cpu = CPU(cache=cache)
+        self.cpu = CPU(cache=cache, clock=clock)
         onbus.append(self.cpu)
         self.ram = RAM(bios)
         onbus.append(self.ram)

@@ -27,6 +27,7 @@ args = {}
 for arg, default, multiple, cast in (("id", None, False, lambda v : v),
                                      ("ram", [], True, lambda v : v),
                                      ("cache", False, False, lambda b : bool(int(b))),
+                                     ("clock", True, False, lambda b : bool(int(b))),
                                      ("screen", True, False, lambda b : bool(int(b))),
                                      ("boot", False, False, lambda b : bool(int(b)))) :
     if multiple :
@@ -73,7 +74,10 @@ class WebSimulator (object) :
         self.play = False
         self.on_stop = []
         self.sim = Simulator()
-        self.ttc = TTC(bios, screen=args["screen"], cache=args["cache"])
+        self.ttc = TTC(bios,
+                       screen=args["screen"],
+                       cache=args["cache"],
+                       clock=args["clock"])
         self.halted = False
         self.step_phase = "boot"
         self.step_index = 0
@@ -165,12 +169,12 @@ class WebSimulator (object) :
     def _ttc_cpu_cycle_enter (self, event) :
         MainView.cycle.step("intr")
     def _ttc_cpu_clock_reset (self, event) :
-        document["clock-tick"].html = "0/16"
+        document["clock-tick"].html = "0"
     def _ttc_cpu_cycle_ALL_enter (self, event, *args) :
         *_, step, _ = event.split(".")
         MainView.cycle.step(step)
     def _ttc_cpu_cycle_clock_exit (self, event, clock) :
-        document["clock-tick"].html = f"{clock}/16"
+        document["clock-tick"].html = f"{clock}"
     def _ttc_cpu_op_ALL_enter (self, event, *args) :
         MainView.cycle.step("exec")
     def _ttc_cpu_intr_set (self, event, num, val) :
@@ -327,7 +331,7 @@ class BusView (object) :
 class CycleView (object) :
     steps = [("boot", "boot", "booting"),
              ("cycle", "intr", "check interrupts"),
-             ("cycle", "clock", 'clock tick (<span id="clock-tick">0/16</span>)'),
+             ("cycle", "clock", 'clock tick (<span id="clock-tick">0</span>)'),
              ("cycle", "fetch", "fetch instruction"),
              ("cycle", "decode", "decode instruction"),
              ("cycle", "exec", "execute instruction"),
@@ -359,7 +363,7 @@ class CycleView (object) :
             else :
                 self.cycle[step].className = "cycle cycle-inactive"
     def clock (self, val) :
-        self.tick.html = f"{val % 16}/16"
+        self.tick.html = f"{val % 16}"
 
 class ScreenView (object) :
     def __init__ (self, width=80, height=24) :